A metal configurable standard cell (MCSC) technology described in U.S. Pat. No. 8,533,641 has dramatically advanced the state of the art of highly integrated application specific integrated circuits (ASICs) and systems on chip (SOCs). In general, devices in accordance with this technology include “fixed” MCSC base cells formed from transistors in underlying layers of a wafer. These base cells can be connected together to form metal configurable standard cells (e.g. NAND gates, buffers, muxes, flip-flops, etc.) using overlying “programmable” metal layer regions that have electrical access to the underlying base cells. Any desired user logic can be further formed by connecting these standard cells together using the programmable metal layers through a conventional ASIC design implementation flow such as synthesis, place and route.
Certain challenges can arise when implementing memories in a metal configurable ASIC design such as an ASIC based on MCSC technology, given that the transistors are primarily fixed in size and pattern and ASIC may be implemented only by changing or configuring a few metal layers. Typically, memories are implemented in these designs using either a hard memory macro or synthesizable RTL. The hard memory macro may be pre-built with a certain memory size (e.g. 10 Kb). So implementing a smaller memory (e.g. 1 Kb) using a 10 Kb hard memory macro is neither area nor power efficient. Meanwhile, using RTL to implement such a memory block might not provide a good solution either as the RTL will synthesize to large array of flip-flops or latches. As a result, the area and power will grow exponentially as the design requirement of the memory increases.
Accordingly, a need remains for a solution to improve area, power, routing efficiency and flexibility when implementing memory in a metal configurable ASIC or similar design.